In memory systems, the capability of sending multiple memory transactions and receiving response from the memory controller is a tool utilized in testing of transaction arbiters in memory controllers and serial IO units or devices such as PCIE (Peripheral Component Interconnect Express), SATA (Serial AT Attachment), and USB (Universal Serial Bus).
However, as interfaces in computer systems increase in speed, certain testing of electronics may be adversely affected because of the inability of a tester to submit multiple memory transactions near in time with each other.
In the operation of a memory controller, there are generally delays between operations because of functioning of the auto response mechanism of the memory controller, the auto response mechanism being a hardware mechanism built into the memory controller to respond to the incoming transactions. Because of this, it has become more difficult to fully stress a system during testing because the memory transactions utilized in the test are separated from each other in time.